DDR3 Memory Module, added information about configuration. Updated Appendix C, Xilinx Design Constraints and Appendix F, Regulatory and Compliance Information. 07/10/2018 1.8.1 03/20/2018 1.8 In Table 1-1, Quad SPI Flash Memory, and [Ref 6], added Micron MT25QL128ABA8ESF-0SIT as a possible part for U7. In Table 1-24, the I2C addresses were updated for the FMC HPC and FMC LPC device rows. 07/08/2016 1.7 Updated VRP/VRN resistor connection information in DDR3 Memory Module. Moved the Additional Resources and Legal Notices appendix to the end of the book. 08/26/2015 1.6.2 In Table 1-9, the I/O standard for SYSCLK_N and SYSCLK_P were updated to LVDS. In Table 1-27, under Directional Pushbutton Switches, the I/O standard for GPIO_SW_C was updated to LVCMOS25. Updated the #USB UART section of Appendix C, Xilinx Design Constraints. 04/13/2015 1.6.1 In HPC Connector J22, the GTX clock count changed from 1 to 2. Updated links. 12/08/2014 1.6 Added a note about jumper header locations below Table 1-1. Cha
BA1EW7-0SIT DFN/6x5 1.7V-2.0V N25Q016A11EF640x MT25QU128ABA1EW7-0SIT DFN/6x5 1.7V-2.0V N25Q032A11ESE40x MT25QU128ABA1ESE-0SIT SO8 Wide 1.7V-2.0V N25Q032A13ESE40x MT25QL128ABA1ESE-0SIT SO8 Wide 2.7V-3.6V SO8 Wide 2.7V-3.6V N25Q032A13ESEC0x N25Q032A13ESF40x MT25QL128ABA8ESF-0SIT SO16 Wide 2.7V-3.6V N25Q032A11EF640E MT25QU128ABA1EW7-0SIT DFN/6x5 1.7V-2.0V N25Q032A13EF640E MT25QL128ABA1EW7-0SIT DFN/6x5 2.7V-3.6V N25Q032A13E1240x MT25QL128ABA8E12-0SIT T-PBGA 2.7V-3.6V N25Q032A13E1241x MT25QL128ABA8E12-1SIT T-PBGA 2.7V-3.6V N25Q064A11ESE40x MT25QU128ABA1ESE-0SIT SO8 Wide 1.7V-2.0V SO8 Wide 1.7V-2.0V SO8 Wide 2.7V-3.6V N25Q064A13ESED0x SO86 Wide 2.7V-3.6V N25Q064A13ESEC0x SO8 Wide 2.7V-3.6V N25Q064A13ESEDFF SO8 Wide 2.7V-3.6V N25Q064A11ESECFF N25Q064A13ESE40x MT25QL128ABA1ESE-0SIT N25Q064A13ESE4MF MT25QL128ABA1ESE-MSIT SO8 Wide 2.7V-3.6V N25Q064A13ESF40E MT25QL128ABA8ESF-0SIT SO16 Wide 2.7V-3.6V N25Q064A13ESF40F MT25QL128ABA8ESF-0SIT SO16 Wide 2.7V-3.6V SO16 Wide 2.7V-3.6V N25Q